Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data, such as a basic input/output system (BIOS), are typically stored in flash memory devices for use in personal computer systems.
Flash memory typically utilizes one of two basic architectures known as NOR Flash and NAND Flash. The designation is derived from the logic used to read the devices. In a NAND type flash memory array architecture, the floating gate memory cells of the memory array are arranged in a matrix of rows and columns. The memory cells of the array are also arranged together in strings, typically of 8, 16, 32, or more each, where the memory cells in the string are connected together in series, source to drain, between a common source line and a column transfer line, often referred to as a bit line. The array is then accessed by a row decoder activating a row of floating gate memory cells by selecting the word line connected to their gates. In addition, bit lines can also be driven high or low depending on the current operation being performed.
As the performance and complexity of electronic systems increase, the requirement for additional memory in a system also increases. However, in order to continue to reduce the costs of the system, it is desirable to keep the parts count low. This can be accomplished by increasing the memory density of an integrated circuit by using such technologies as multilevel cells (MLC). For example, MLC NAND flash memory is a cost effective non-volatile memory.
Multilevel memory cells assign a data state (e.g., as represented by a bit pattern) to a specific range of threshold voltages (Vt) stored on the memory cell. Single level memory cells (SLC) permit the storage of a single bit of data on each memory cell. Meanwhile, MLC technology permits the storage of two or more bits per cell (e.g., 2, 4, 8, 16 bits), depending on the quantity of threshold voltage ranges assigned to the cell and the stability of the assigned threshold voltage ranges during the lifetime operation of the memory cell. The number of threshold voltage ranges (e.g., levels), which are sometimes referred to as Vt distribution windows, used to represent a bit pattern comprised of N-bits is 2N. For example, one bit may be represented by two levels, two bits by four levels, three bits by eight levels, etc.
For example, a cell may be assigned a Vt that falls within one of four different voltage ranges of 200 mV, each being used to represent a data state corresponding to a bit pattern comprised of two bits. Typically, a dead space (which is sometimes referred to as a margin) of 0.2V to 0.4V is maintained between each range to keep the Vt distributions from overlapping. If the voltage stored on the cell is within the first of the four Vt distributions, the cell in this case is storing a logical ‘11’ state and is typically considered the erased state of the cell. If the voltage is within the second of the four Vt distributions, the cell in this case is storing a logical ‘10’ state. A voltage in the third distribution of the four Vt distributions would indicate that the cell in this case is storing a logical ‘00’ state. Finally, a Vt residing in the fourth Vt distribution indicates that a logical ‘01’ state is stored in the cell.
There are advantages and disadvantages associated with using SLC or MLC memory. MLC memory is generally considered more cost effective in regards to memory density as MLC memory can, for example, store multiple bits of data in a single memory cell as opposed to SLC memory which is conventionally used to store one bit of data per cell. However, conventional SLC memory can be written to many (e.g., by an order magnitude) more times than conventional MLC memory. For example, a characteristic of conventional MLC memory is that after data has been erased and re-written about 10,000 times the memory may become subject to significant read and write errors. Conventional SLC memory on the other hand typically may be erased and re-written about 100,000 times before the reliability of the data begins to deteriorate. These density and performance characteristics also apply between different types of MLC arrays. MLC devices with four and eight levels exist today, while denser memories are being researched. While an MLC with more levels would be more efficient (higher density) than an MLC with less levels (lower density), these higher density devices may have performance penalties over the lower density devices. The case of a device built with SLC (two level) and MLC (more than two level) can be generalized as a device with multiple memory arrays, each with its own density and performance trade-offs. An example is a device built with an array of MLC (four level) and an array of MLC (eight level). There could even be more than two arrays of memories, such as SLC, MLC (four level) and MLC (eight level). A common naming convention is to refer to SLC memory as MLC (two level) memory as SLC memory utilizes two levels in order to store one bit of data as represented by a 0 or a 1, for example. MLC memory configured to store two bits of data can be represented by MLC (four level), three bits of data by MLC (eight level), etc. An MLC (four level) memory cell is typically referred to as a lower density memory cell than an MLC (eight level) memory due to the lower number of bits stored per memory cell, for example. SLC (e.g., MLC (two level)) is typically referred to as a lower density memory than MLC (four level) memory and so on.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for hybrid memory devices that are adapted to manage the utilization of memory of different densities, such as SLC and MLC memory, to take advantage of preferred operating characteristics associated with each type of memory.